A basic complementary metal oxide semiconductor (CMOS) switch comprises an N-channel transistor in parallel with a P-channel transistor. The sources of the N- and P-channel transistors comprise an input of the switch, and the drains of the N- and P-channel transistors comprise an output of the switch. The gates of the N- and P-channel transistors are coupled to complementary enable signals that control the state of the CMOS switch. An enable signal is coupled to the gate of the N-channel transistor, and a complement of the enable signal is coupled to the gate of the P-channel transistor. When an enable signal is logic high, the switch is “on” the switch samples the input voltage. When the enable signal is logic low, the switch is “off”.
The main sources of leakage in the off-state are the sub-threshold leakage current and the gate-induced drain leakage (GIDL) current. GIDL current is caused by high field effect in the drain junction of metal oxide semiconductor (MOS) transistors. GIDL depends on drain-to-body voltage and drain-to-gate voltage. In some applications, GIDL current dictates performance of the system. For example, a circuit can include several CMOS switches coupled to a common terminal (e.g., a multiplexer or de-multiplexer) such that, during operation, only one CMOS switch is in the on-state and the rest of the CMOS switches are in the off-state. In such case, the GIDL currents combine and scale based on the number of switches in the off-state. The combined GIDL current can significantly impact performance of the system, particularly if the CMOS switches are operated as analog switches.